1. Field of the Invention
The present invention relates to a frame communication system, and in particular to a frame communication system composed of a code converter and a frame generator/decomposer.
Recently, developments in a communication field have been remarkable so that even for information transfer, an essentially different cell-based transfer mode has been newly adopted in addition to the prior art character-based or frame-based transfer mode. In any transfer mode, it is important to efficiently transmit, data, and even in the most basic frame-based transfer mode an efficient data transfer between e.g. different frame-based transfer modes is required.
2. Description of the Related Art
FIG. 15 shows an arrangement of the prior art network. This network is composed of interface nodes 41_1–41_5 (occasionally represented by a reference numeral 41) connected with a 50M ring-like transmission line 40, Ethernets 44_1–44_6 connected to the interface nodes 41_1–41_5.
The interface node 41 is composed of a synchronous line multiplexer 42 and an Ethernet accommodation LS (Line Set) 43.
The Ethernet 44_1, for example, is connected to the Ethernet 44_6 through the interface node 41_1, the 50M ring transmission line 40, and the interface node 41_5. The Ethernet accommodation LS 43 of the interface node 41_1 is connected to the Ethernet accommodation LS 43 of the interface node 41_5 by a P—P connection (point to point connection).
FIG. 16 shows an arrangement of the interface node 41_1 and the 50M ring transmission line 40 shown in FIG. 15 in more detail. The 50M ring transmission line 40 is composed of a #0 system optical transmission line 40_1 and a #1 system optical transmission line 40_2. The synchronous line multiplexer 42 is composed of a #0 optical IF 42_1, a #1 optical IF 42_2, and a control-monitor clock portion 45. The Ethernet accommodation LS 43 is composed of terminal IF portions (interfaces) 43_1, 43_2, etc.
The #0 optical IF 42_1 and the #1 optical IF 42_2 are composed of an O/E•E/O converter 51, an SDH processor 52, a line multiplexer 53, an FIFO 54, and an 8-1 SEL portion (selector) 55. The control-monitor clock portion 45 is composed of a PLO (Phase Locked Oscillator) 56 and a controller-monitor 57. The terminal IF portions 43_1 and 43_2 are composed of an HW interface 61 connected to the, synchronous line multiplexer 42, a terminal interface 62 connected to the Ethernet 44, and a controller-monitor 63.
In operation, after optoelectronic conversion is performed at the O/E•E/O converter 51 to the data on an SDH frame of e.g. the #0 system optical transmission line 40_1, the data are sent to the terminal interface 62 through the SDH processor 52, the line multiplexer 53, and the HW interface 61 of the terminal IF portion 43_1. At the terminal interface 62, the data are put on an Ethernet frame to be transmitted to the Ethernet 44_1.
On the other hand, the data on the frame of the Ethernet 44_1 are transmitted to the O/E•E/O converter 51 through the terminal interface 62, the HW interface 61, the 8-1 SEL portion 55 of the #0 optical IF portion 42_1, the line multiplexer 53, and the SDH processor 52. Then, electrooptic conversion is performed to the data at the O/E•E/O converter 51, so that the data are carried on the SDH frame of the #0 system optical transmission line 40_1.
FIG. 17 shows the terminal IF portion (Ethernet accommodation LS) 43 shown in FIG. 16 in more detail.
This Ethernet accommodation LS 43 composes a transmission interface by a line IF portion 10, a check data generator 11, a transmitting buffer 13, a transmitting buffer write controller 14, a transmitting buffer read controller 15, a data checker 16, and a capsule disassembler 19.
Also, the Ethernet accommodation LS 43 composes a reception interface by a capsule assembler 38, a data checker 32, a receiving buffer 34, a receiving buffer write controller 35, a receiving buffer read controller 36, a data checker 37, and a line IF portion 10.
Furthermore, the Ethernet accommodation LS 43 has an available bandwidth enable generator 23 and an available bandwidth setter 24 common to both of the transmitting and the receiving sides.
In operation, the line IF portion 10 receives a variable length frame from an accommodated line to be converted into an NRZ (Non Return Zero) signal. Then, the signal is outputted as transmitting data to the transmission line side.
The check data generator 11 adds check data to the transmitting data. The transmitting buffer write controller 14 performs a control to write the data in the transmitting buffer 13 for rate conversion.
The available bandwidth enable generator 23 generates an available bandwidth enable signal 84 based on a setting value 96 preset at the available bandwidth setter 24, a transmitter frame pulse 88, and a transmission line clock 89. This signal 84 enables the transmitting buffer read controller 15 to control reading the data from the transmitting buffer 13 so that the data checker 16 checks the read data.
The capsule disassembler 19 encapsulates the read data based on the enable signal 84 to provide the transmission line output data 87. Thus, the variable length frame on the accommodated line is encapsulated and accommodated in the available bandwidth of the transmission line.
FIGS. 18A–18C show a concept of a check data addition and encapsulation. FIG. 18A shows a variable length frame from the accommodated line. FIG. 18B shows a variable length frame to which check data 71 such as horizontal parity or CRC are added.
This variable length frame is disassembled, and then encapsulated. FIG. 18C shows a capsule of the i-th disassembled portion, which is composed of a header portion 72 and a frame accommodating area portion 73.
The header portion 72 is further composed of a use/non-use portion 74, a frame classification portion 75, and a valid frame length portion 76. The use/non-use portion 74 indicates whether or not there is an Ethernet frame to be accommodated on the transmission line. The frame classification portion 75 indicates whether the data of the frame accommodating area portion 73 include the head of the frame, the intermediate portion of the frame, or the end of the frame, or assume a single frame.
The valid frame length portion 76 includes the information indicating up to where in the frame accommodating area portion 73 the valid data exist, the information being valid only when it is accommodated at the end frame or a single frame.
The frame accommodating area portion 73 accommodates actual data such as a frame from the accommodated line and check data.
FIG. 19 shows an STM0/OC1 frame format of a well-known SDH/SONET. This frame is composed of an SOH portion of 9 lines and 3 rows, a POH portion of 9 lines and 1 row, and a payload portion of 9 lines and 86 rows. The payload portion is composed of byte batch time slots TS0–TS85, TS90–TS175, . . . , TS720–TS805.
For example, the variable length frame of the Ethernet is preliminarily allocated with 5 bytes TS91–TS95 for an accommodated area. This allocation can be performed by the control/monitor terminal shown in FIG. 15.
In FIG. 17, the capsule assembler 37 assembles the encapsulated transmission line input data 90, and then instructs the receiving buffer write controller 35, based on the available bandwidth enable signal 92, to perform a control in order to write the assembled data in the receiving buffer 34. At this time, the data checker 32 performs data check for the assembled data.
The receiving buffer read controller 36 controls reading the data from the receiving buffer 34 so that the read data are transmitted to the line IF portion 10 through the data checker 37. At this time, the data checker 37 performs error check for the read data.
The line IF portion 10 accommodates the received data in the Ethernet frame to be transmitted to the accommodated line.
In such a prior art frame communication system, an overhead such as a header for encapsulation worsens the line efficiency.